1. Field of the Invention
The present invention relates to thin film transistors (TFTs) and manufacturing methods thereof, and, more particularly, to a MOS silicon thin film transistor and a manufacturing method thereof.
2. Description of the Background Art
So far, a static random access memory (hereinafter referred to as a SRAM) is known as a semiconductor memory device. FIG. 59 is a circuit diagram illustrating an example of a memory cell in a conventional SRAM. Referring to FIG. 59, a memory cell 180 includes a CMOS flip-flop connected between a power supply Vcc and ground Vss and NMOS field effect transistors Q5 and Q6 for accessing connected between a bit line 181 and the flip-flop and between a bit line 182 and the flip-flop, respectively.
The flip-flop includes first and second CMOS inverters which are cross-coupled. One of the inverters is implemented with a PMOS thin film transistor Q1 and an NMOS drive field effect transistor Q2, and the other is implemented with a PMOS thin film transistor Q3 and an NMOS drive field effect transistor Q4. Gates of transistors Q5 and Q6 are connected to a word line 183.
FIG. 60 is a plan view of a conventional semiconductor device (SRAM) having a thin film transistor (TFT). FIG. 61 is a sectional view of the semiconductor device illustrated in FIG. 60 taken along line 61--61. The sectional structure of the semiconductor device having a TFT illustrated in FIG. 61 is disclosed, for example, in IEEE Electron Device Letters (Vol. EDL-4, No. 8, P-272-274, 1983) and Denshi Joho Tsushin Gakkai Gijyutsu Kenkyu Hokoku (Vol. 89, No. 67, P-1-6, 1989) and so on.
Referring to FIGS. 60 and 61, a conventional semiconductor device having a TFT includes a silicon substrate 201, a P-well 202 formed on the surface of silicon substrate 201, element isolating regions 204 formed spaced a predetermined distance apart from each other in a predetermined region in P well 202, p-type impurity regions 203 formed beneath element isolating regions 204, respectively, low concentration impurity regions 209a formed spaced beneath element isolating from each other between adjacent element isolating regions 203, a high concentration impurity region 207a formed to be continuous with one end of low concentration impurity region 209a, a gate electrode 206a formed on semiconductor substrate 201 between adjacent high concentration impurity regions 207a with a gate oxide film 205a interposed therebetween, and sidewalls 208a formed on both sidewall parts of gate electrode 206a.
The conventional semiconductor device having a TFT further includes an impurity region 210 formed in another region isolated by an element isolating oxide film 204 on the surface of semiconductor substrate 201, an impurity region 218 formed spaced a predetermined distance apart from impurity region 210, high concentration impurity regions 209b formed to be continuous with impurity regions 210, 218, respectively, low concentration impurity regions 207b formed to be continuous with high concentration impurity regions 209b, respectively, a gate electrode 206b formed on semiconductor substrate 201 between impurity region 210 and impurity region 218 with a gate insulating film 205b interposed therebetween, and sidewalls 208b formed on both sidewall parts of gate electrode 206b.
The conventional semiconductor device having a TFT further includes a contact electrode 211 formed to be electrically in contact with impurity region 210, a polycrystalline silicon film 215 (215a, 215b) electrically connected to contact electrode 211 and formed to extend onto an interlayer insulating film 212, a gate electrode 213 formed under a channel region 215 in polycrystalline silicon film 215 with a gate oxide film 214 interposed therebetween, an interlayer insulating film 216 formed to cover the whole surface and having an opening on impurity region 218, a barrier metal layer 219 formed to be electrically connected to impurity region 218 in a contact part 217 and to extend onto interlayer insulating film 216, an aluminum interconnection 220 formed on barrier metal layer 219, and a passivation film (PSG film) 221 formed on aluminum interconnection 220.
An N-type MOS transistor is implemented with a pair of impurity regions 207a (209a), gate oxide film 205a, and gate electrode 206a. In addition, an N-type MOS transistor is implemented with impurity region 210, impurity region 218, gate oxide film 205b, and gate electrode 206b. A TFT transistor is implemented with gate electrode 213, gate oxide film 214, and polycrystalline silicon film 215. Specifically, channel region 215a and a pair of source/drain regions 215b of the TFT transistor are formed in polycrystalline silicon film 215.
FIGS. 62 to 72 are sectional views for describing a manufacturing process (a first step to an eleventh step) of the conventional semiconductor device having a TFT illustrated in FIG. 61. Now, referring to FIGS. 61 to 72, a manufacturing process of the conventional semiconductor device having a TFT will be described.
First, as illustrated in FIG. 63, a P-well 202 is formed on an N-type semiconductor substrate 201 in a state illustrated in FIG. 62. P-type impurity regions 203 and element isolating oxide films 204 are formed in predetermined regions on the surface of P-well 202.
Next, as illustrated in FIG. 64, a polycrystalline silicon film 206 is formed on the whole surface. Resists 222 are formed in predetermined regions on polycrystalline silicon film 206. Then, as illustrated in FIG. 65, polycrystalline silicon film 206 is etched using resist films 222 (See FIG. 64) as a mask to form gate electrodes 206a and 206b. Ion implantation is carried out on semiconductor substrate 201 using gate electrodes 206a, 206b as a mask to form low concentration impurity regions 207a, 207b. Sidewalls 208a, 208b are formed on both sidewall parts of gate electrodes 206a, 206b. Ion implantation is carried out on semiconductor substrate 201 using gate electrodes 206a, 206b and sidewalls 208a, 208b as a mask to form high concentration impurity regions 209a, 209b.
As described above, adjacent two N-type MOS transistors are formed.
Next, as illustrated in FIG. 66, an interlayer oxide film 212a is formed on the whole surface. A contact electrode 211 is formed to be electrically connected to one of high concentration impurity regions 209b through an opening in interlayer oxide film 212a. An impurity region 210 is formed by carrying out heat treatment.
Next, as illustrated in FIG. 67, an interlayer oxide film 212b is formed on the whole surface. A gate electrode 213 of a TFT is formed on interlayer oxide film 212b in a region above gate electrode 206a.
Next, as illustrated in FIG. 68, a gate oxide film 214 of the TFT is formed on the whole surface. A contact part is opened in interlayer insulating film 212b and gate oxide film 214 on contact electrode 211.
Next, as illustrated in FIG. 69, a polycrystalline silicon film 215 is formed to be electrically connected to contact part 211 and to extent onto gate electrode 213 with gate oxide film 214 interposed therebetween. N-type impurities are implanted into polycrystalline silicon film 215.
Next, as illustrated in FIG. 70, a resist 223 is formed on a channel region 215a in polycrystalline silicon film 215 (215a, 215b). P-type impurities (BF.sub.2.sup.+) are ion-implanted into polycrystalline silicon film 215 (215b) using resist 223 as a mask. Source/drain regions 215b of the TFT are formed by doing this.
Next, as illustrated in FIG. 71, resist 223 (See FIG. 70) is removed, and then an interlayer insulating film 216 is formed on the whole surface. An opening 216a is formed in a region in interlayer insulating film 216 on high concentration impurity region 209b not connected with contact electrode 211 N-type impurities are implanted into the surface of semiconductor substrate 201 exposed in opening 216a. An impurity region 218 is formed by doing this.
Next, as illustrated in FIG. 72, a barrier metal layer 219 is formed in a contact part 217 to be electrically connected to impurity region 218 and to extend onto interlayer insulating film 216. Aluminum interconnection 220 is formed on barrier metal layer 219 using a sputtering process.
Finally, as illustrated in FIG. 61, a passivation film (PSG film) 221 is formed on aluminum interconnection 220.
The conventional semiconductor device having a TFT was completed as described above.
As described above, channel region 215a and source/drain regions 215b of the TFT are formed in polycrystalline silicon film 215 in the conventional semiconductor device having a TFT.
FIG. 73 is an enlarged plan view of the TFT part illustrated in FIG. 61. FIG. 74 is a sectional view of the TFT part illustrated in FIG. 73. Referring to FIGS. 73 and 74, the leakage current is larger on the occasion when it is OFF is larger as the surface area of a junction part 215c of channel region 215a and source/drain region 215b in the channel width direction is larger in the conventional TFT.
Specifically, the junction boundary of junction part 215c has a crystal structure in which a plurality of silicon crystals are combined. If the surface area of the plurality of silicon crystals combined on the junction boundary becomes large, the leakage current is also increased on the occasion when the transistor is OFF.
So far, it is proposed to reduce the thickness of the whole of polycrystalline silicon 215c) as an approach for this.
However, if the thickness of polycrystalline silicon film 215 (215a, 215b, 215c) is reduced, the implantation energy must be made extremely low in order to prevent penetration of impurities when impurities are ion-implanted into source/drain regions 215b. Therefore, there was a problem that uniformity of the implantation amount of ions is degraded. In addition, there was also a problem that a long time is required for the implantation process if implantation is carried out with low energy.
In addition, in a case where source/drain region 215b is extended and used as an interconnection layer, there was disadvantage that the resistance of the interconnection layer is made high by reducing the thickness of polycrystalline silicon film 215 (215a, 215b, 215c). As a result, there was a problem that it is not possible to realize speeding up of the transistor.
Specifically, so far, there were problems that a long time is required when impurities are introduced into source/drain regions 215 if the thickness of polycrystalline silicon film 215 is reduced in order to reduce the leakage current on the occasion when the TFT transistor is OFF, the resistance of the interconnection layer connected to source/drain region 215b becomes high, and so on. As a result, it was difficult to reduce the leakage current and lower the resistance of an interconnection layer connected to the source/drain region in the conventional TFT (Thin Film Transistor).